ELE523E Computational Nanoelectronics, Fall 2014
Presentation Rules and Topics
Each student makes his/her presentation in 30 minute time span, 20 minutes for the
presentation and 10 minutes for the questions/comments.
Presentation topics and corresponding papers are listed below. The presentations should
be mainly constructed on the listed papers; however it is encouraged to use/refer other
papers and sources.
Students should decide their presentation topics by 10/11/2014. We will finalize the
presentation schedule during the lecture time on 10/11/2014.
All students, not just the presenter, are expected to read the related papers before
presentations. Students are expected to ask (tough) questions to the presenter.
Students are graded considering the presentation clarity/quality and also the presenter’s
knowledge on the topic.
W12 (24/11/14) TOPICS:
o W12-P1, Onurcan Erdoğan, Quantum Circuit Design: Maslov, D., Dueck, G. W., &
Miller, D. M. (2005). Toffoli network synthesis with templates. Computer-Aided Design
of Integrated Circuits and Systems, IEEE Transactions on, 24(6), 807-817.
o W12-P2, Ebru Gür, Quantum Circuit Reliability: Knill, E. (2005). Quantum
computing with realistically noisy devices. Nature,434(7029), 39-44.
o W12-P3, Ceylan Morgül, Spintronics: Manipatruni, S., Nikonov, D. E., & Young, I. A.
(2012). Modeling and Design of Spintronic Integrated Circuits. Circuits and Systems I:
Regular Papers, IEEE Transactions on, 59(12), 2801-2814.
o W12-P4, Serter Yavuz, DNA Computing: Elbaz, J., Lioubashevski, O., Wang, F.,
Remacle, F., Levine, R. D., & Willner, I. (2010). DNA computing circuits using libraries
of DNAzyme subunits.Nature nanotechnology, 5(6), 417-422.
W13 (1/12/14) TOPICS:
o W13-P1, Melek Şerifoğlu, Nanoarray based Computing: Strukov, D. B., & Likharev,
K. K. (2012). Reconfigurable nano-crossbar architectures. Nanoelectronics, R. Waser,
o W13-P2, Emre Duman, Nanoarray based Computing: DeHon, A. (2003). Array-based
architecture for FET-based, nanoscale electronics. Nanotechnology, IEEE Transactions
on, 2(1), 23-32.
o W13-P3, Mustafa Çelik, Stochastic Computing: Chen, H., & Han, J. (2010, May).
Stochastic computational models for accurate reliability evaluation of logic circuits.
In Proceedings of the 20th symposium on Great lakes symposium on VLSI (pp. 61-66).
o W13-P4, Ensar Vahapoğlu, Probabilistic Bayesian Networks: Rejimon, T., & Bhanja,
S. (2005, August). Scalable probabilistic computing models using Bayesian networks.
In Circuits and Systems, 2005. 48th Midwest Symposium on (pp. 712-715). IEEE.
W14 (8/12/14) TOPICS:
o W14-P1, Nergiz Şahin, Defects in Quantum Cellular Automata: Tahoori, Mehdi
Baradaran, et al. "Defects and faults in quantum cellular automata at nano scale." VLSI
Test Symposium, 2004. Proceedings. 22nd IEEE. IEEE, 2004.
o W14-P2, Onur Tunalı, Defect Tolerance for Nanoarrays: Hogg, T., & Snider, G.
(2008). Defect-tolerant logic with nanoscale crossbar circuits. In Emerging
Nanotechnologies (pp. 5-32). Springer US.
o W14-P3, Umut Yılmazer, Defect Tolerance for Nanoarrays: Huang, J., Tahoori, M.
B., & Lombardi, F. (2004, October). On the defect tolerance of nano-scale twodimensional crossbars. In Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004.
Proceedings. 19th IEEE International Symposium on (pp. 96-104). IEEE.

ELE523E Computational Nanoelectronics, Fall 2014 Presentation